1. Field of Invention
This invention relates to a multi-chips package. More particularly, the present invention is related to a multi-chips package having a reinforced device for preventing the bumps, which connects the chip and the substrate, from being damaged and cracked.
2. Related Art
Recently, integrated circuit (chip) packaging technology is becoming a limiting factor for the development in packaged integrated circuits of higher performance. Semiconductor package designers are struggling to keep pace with the increase in pin count, size limitations, low profile, and other evolving requirements for packaging and mounting integrated circuits.
Due to the assembly packages in miniature and the integrated circuits operation in high frequency, MCM (multi-chips module) packages are commonly used in said assembly package and electronic devices. Usually, said MCM package mainly comprises at least two chips encapsulated therein, for example a processor unit, a memory unit and related logic units, so as to upgrade the electrical performance of said assembly package. In addition, the electrical paths between the chips in said MCM package are short so as to reduce the signal delay and save the reading and writing time.
Generally speaking, conventional multi-chips module (MCM) packages shall be a multi-chips side-by-side package or a multi-chips stacked package. As shown in FIG. 1, it illustrates a multi-chips stacked package and said stacked package is formed by disposing an upper chip 110 on an upper surface 124 of a substrate 120 having an opening 122 formed therein by flip-chip bonding, disposing a lower chip 130 in the opening 122 and flip-chip bonding to the upper chip 110 so that the upper chip 110 covers the opening 122 and the lower chip 130. Generally speaking, the upper chip 110 and the lower chip 130 may be a memory chip and a logic chip respectively. In such an arrangement, the electrical signals generated from the memory chip and the logic chip are able to be integrated in the assembly package and then transmitted to external electronic devices through the solder balls 128 formed on the lower surface 126 of the substrate 120. Although such design can reduce the overall thickness of the assembly package and upgrade the electrical performance, the bumps 160 for connecting the upper chip 110 and the substrate 120 will be easily damaged due to the coefficient of thermal expansion of the upper chip 110 and the coefficient of thermal expansion of the substrate 120 are different from each other. As mentioned above, the coefficient of thermal expansion of the substrate 120 is about 16*10−6 ppm/° C. and the coefficient of thermal expansion of the upper chip is about 4*10−6 ppm/° C. Accordingly, the effect of CTE mismatch will cause the bumps 160 connecting the substrate 110 and the upper chip 120 easily damaged.
Therefore, providing another assembly package to solve the mentioned-above disadvantages is the most important task in this invention.